1. Technical Field
Various embodiments relate generally to a semiconductor apparatus, and more particularly, to a test mode of a semiconductor apparatus.
2. Related Art
A semiconductor apparatus typically employs a clock synchronous system to adjust operation timing in order to satisfy a high-speed operation without error. However, a semiconductor apparatus operating as a clock asynchronous system such as mobile DRAM is still used when necessary. The clock asynchronous semiconductor apparatus processes a received signal and data according to a delay amount set therein. However, due to process, voltage, and temperature (PVT) effects or the like, data may not be outputted at a desired time. Since a controller is utilized during a normal operation to control the clock asynchronous semiconductor apparatus when processing data outputted from the semiconductor apparatus in consideration of the aforementioned effects, data may be outputted at a desired time.
FIG. 1 is an operation waveform diagram of a conventional clock asynchronous semiconductor apparatus.
The semiconductor apparatus outputs data at a time according to a preset CAS latency (CL) during a read operation. The CL indicates the number of clock cycles between when an external read command RDCMD is inputted and when a first data is outputted, based on an external clock signal CLK.
The clock asynchronous semiconductor apparatus receives the external read command RDCMD from an external controller in synchronization with the external clock signal CLK. Then, the clock asynchronous semiconductor apparatus delays the external read command RDCMD by the CL based on the delay amount set therein, and outputs the delayed signal as an output enable flag signal OEFLAG. The delayed signal is not outputted immediately when the output enable flag signal OEFLAG is activated, but is rather outputted after a delay amount tREP based on an internal data output path of the semiconductor apparatus.
The delayed signal is further delayed by the delay amount based on the internal data output path after the CL. Furthermore, since the delay amount is influenced by PVT variation, the data output time cannot be controlled precisely.
During the normal operation, however, the controller, as described above, may control the semiconductor apparatus processes data in consideration of the aforementioned effects, thereby outputting data when desired. However, when a test device does not have the same function as the controller while the semiconductor apparatus is being tested, the test device cannot accurately recognize and analyze data outputted from the clock asynchronous semiconductor apparatus.